1. Field of the invention:
This invention relates generally to logic gates employed in N-channel MOS integrated circuits and, more particularly, but not by way of limitation, to an improved gate for use in an N-channel MOS integrated circuit operating in response to a clock having four phases, each of which has one, but only one, other phase which does not overlap therewith, the improved gate exhibiting improved response characteristics.
2. Prior Art Statement:
In general, logic gates employed in N-channel MOS integrated circuits have been designed to operate within the timing constraints inherent in a particular clock structure. For example, a gate designed to have satisfactory response characteristics in a two phase clock structure may be unable to perform satisfactorily in a four phase clock structure. Similarly, a gate which performs satisfactorily in a four phase clock structure wherein every phase has one, but only one, other phase which does not overlap therewith, may exhibit less than satisfactory performance in a four phase clock structure wherein every phase overlaps every other phase. However, for a particular type of clock structure, such as the four phase clock structure within which the present invention is designed to operate, it is generally desirable that a gate eliminate or, at least, minimize the amount of overlap between the output signal provided by the gate and the clock phases which normally do not overlap the clock phase being gated. By way of contrast, an exemplary prior art gate has been included in the drawings, together with comparative response waveforms.